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| CABS ADC in 0.13μm CMOS. |
This research project was conducted with Mr. Octavian Stelescu as part of his M.A.Sc. research.
From Octavian’s abstract:
This work examines the development of an 8-bit analog to digital converter (ADC) using the comparator assisted binary search (CABS) based architecture. The CABS ADC is a hybrid structure between the Flash ADC and the successive approximation register (SAR) ADC, capable of achieving excellent energy per conversion in the order of femto Joules. The architecture relies on a post fabrication calibration strategy to correct for process variation tolerances (PVT) and establish comparator threshold levels.
From simulation results the 8-bit ADC is capable of achieving a resolution of 7.98 bits at DC with a maximum frequency of operation of 20 MHz and an excellent figure of merit (FOM) of only 15.8 fJ per conversion. The input range is 600 mV differential, and the integral nonlinearity (INL) and the differential nonlinearity (DNL) are within 1/2LSB. The effective resolution bandwidth (ERBW) achieved is 25MHz with a signal to noise and distortion ratio (SINAD) of 49.1 dB and a spurious free dynamic range (SFDR) of 66.3dB. The core power consumption without output latches and drivers is only 122 μW for a sampling frequency of 20 MHz. The ADC was fabricated in a 0.13 μm IBM CMOS eight metal layer process (CMRF8SF). The use of an external sample-and-hold (SAH) in the measurement phase of the fabricated ADC places an upper limit on the maximum frequency of operation of the ADC. The measured FOM at a sampling frequency of 25 MHz is 15 fJ with a core power consumption of 100 μW.Using a non-optimum calibration code the INL of the fabricated ADC was improved from 64 LSB to 11 LSB. The DNL was improved from -68 LSB to 14 LSB. The ENOB was improved to 5.1 bits from 3.1 bits. The SINAD was 32.3 dB and the SFDR was 35.7 dB for an input frequency of 50 kHz at a sampling frequency of 4 MHz.
