Friday, May 18, 2012

CABS-based ADC

CABS ADC in 0.13μm CMOS.
This research project was conducted with Mr. Octavian Stelescu as part of his M.A.Sc. research.

From Octavian’s abstract:

This work examines the development of an 8-bit analog to digital converter (ADC) using the comparator assisted binary search (CABS) based architecture. The CABS ADC is a hybrid structure between the Flash ADC and the successive approximation register (SAR) ADC, capable of achieving excellent energy per conversion in the order of femto Joules. The architecture relies on a post fabrication calibration strategy to correct for process variation tolerances (PVT) and establish comparator threshold levels.


From simulation results the 8-bit ADC is capable of achieving a resolution of 7.98 bits at DC with a maximum frequency of operation of 20 MHz and an excellent figure of merit (FOM) of only 15.8 fJ per conversion. The input range is 600 mV differential, and the integral nonlinearity (INL) and the differential nonlinearity (DNL) are within 1/2LSB. The effective resolution bandwidth (ERBW) achieved is 25MHz with a signal to noise and distortion ratio (SINAD) of 49.1 dB and a spurious free dynamic range (SFDR) of 66.3dB. The core power consumption without output latches and drivers is only 122 μW for a sampling frequency of 20 MHz. The ADC was fabricated in a 0.13 μm IBM CMOS eight metal layer process (CMRF8SF). The use of an external sample-and-hold (SAH) in the measurement phase of the fabricated ADC places an upper limit on the maximum frequency of operation of the ADC. The measured FOM at a sampling frequency of 25 MHz is 15 fJ with a core power consumption of 100 μW.Using a non-optimum calibration code the INL of the fabricated ADC was improved from 64 LSB to 11 LSB. The DNL was improved from -68 LSB to 14 LSB. The ENOB was improved to 5.1 bits from 3.1 bits. The SINAD was 32.3 dB and the SFDR was 35.7 dB for an input frequency of 50 kHz at a sampling frequency of 4 MHz.


Thursday, May 17, 2012

Distributed Bidirectional Amplifiers in CMOS

This research was conducted along with Dr. Ziad El-Khatib as part of his Ph.D. program. From Ziad's abstract:

A highly-linear transmitter with fully-integrated broadband design linearization capabil- ity is required to address linearity improvements. When the input signal driven into the amplifier semiconductor is increased, the output is also increased until a point where dis- tortion products can no longer be ignored. The harmonics and higher order distortion of the output signal are generated by nonlinearities of MOSFET devices. In response to the need to correct the broadband distributed amplifier (DA)’s nonlinear distortion, a num- ber of DA linearization techniques have been developed. However, most of the published DA linearization methods reported do not provide fully-integrated distortion cancellation techniques with large third-order intermodulation (IM3) distortion reduction.


The main contributions of this thesis research is the realization a fully-integrated high- frequency active broadband linearizer for large IM3 distortion cancellation and spectral regrowth reduction in standard CMOS technology.


In this thesis, we demonstrate a fully-integrated fully-differential linearized CMOS dis- tributed bidirectional amplifier that achieves large IMD3 distortion reduction over broad- band frequency range for both RF paths. The proposed linearized bidirectional DA has the drain and gate transmission-lines stagger-compensated. Reducing the DA IM3 distortion by mismatching the gate and drain LC delay-line ladders. The proposed fully-differential linearized DA employs a cross-coupled compensator transconductor to enhance the linearity of the DA gain cell with a nonlinear drain capacitance compensator for wider linearization bandwidth. The proposed linearized CMOS bidirectional DA achieves a measured IM3 distortion reduction of 20 dB with frequency of operation from 0.1 GHz to 9.5 GHz and a two-way amplification of 5 dB in both RF directions. The proposed linearized DA is imple- mented in 0.13μm RF CMOS process for use in highly-linear broadband communication.