2012 Summer Research

This summer I'm working with this year's capstone award winning team that produced the MuscleMate electromyographic gesture recognition system. We are attempting to bring the device closer to  commercialization. Over the course of a fourth year project it is difficult to even complete one prototype, let alone produce a prototype that could go into mass production. The work that we're undertaking this summer fine tunes the design and is replacing some major subsystems within our overall product.

Capstone Project 2011-2012

An electromyography hardware acquisition unit was designed using commodity components with a view towards future full-scale ASIC integration. Surface electromyography was accomplished at forearm muscle sites using both dry and Ag/AG-CL differential electrodes. The acquired signal was amplified differentially and then processed using a combination of a bandpass filter and a dual notch filter. The filters were implemented using eighth-order switch capacitor filters with a reference clock frequency of 20 kHz. The bandpass filters retained the salient electromyographic frequencies of 20 Hz to 120 Hz. The notch filters were placed at the problematic 60 Hz and 120 Hz powerline interference frequencies. The processed analog signals were digitized using an eight bit analog-to-digital converter and then further processed for frequency content within a microcontroller. Bluetooth was used to transfer data from the microcontroller to a variety of Bluetooth enabled hardware devices including smart phones and laptops. Gesture recognition software implemented using support vector machines interpreted both the muscle activity intensity and the sequencing of muscle activation thereby providing gesture recognition. The system was designed to accommodate up to six sensors but the number of sensors can be increased by multiplexing inputs. Due to the inherent train-ability of support vector machines, the implemented gesture recognition algorithm may be trained for various applications as well as for different users of the implemented system.

New Book: Distributed CMOS Bidirectional Amplifiers

One of my graduating Ph.D. students, Dr. Ziad El-Khatib, along with myself and my colleague Dr. Samy Mahmoud, has a new book. As Springer describes it, the book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications. A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems.

You will find that the book:

• Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells;
• Presents most recent techniques for linearization of CMOS distributed amplifiers;
• Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling;
• Includes circuit applications for UWB Radio-over-Fiber networks.

Content Level » Research

Keywords » Analog Circuits - Analog Circuits and Signal Processing - CMOS Bidirectional Distributed Amplifier - CMOS Distributed Amplifier - Distributed Amplifier - Distributed Circuit Design - Linearized CMOS Distributed Amplifier - On-chip Inductor Integration - Radio over Fiber -UWB Radio over Fiber

CABS-based ADC

CABS ADC in 0.13μm CMOS.

This research project was conducted with Mr. Octavian Stelescu as part of his M.A.Sc. research.

From Octavian’s abstract:

This work examines the development of an 8-bit analog to digital converter (ADC) using the comparator assisted binary search (CABS) based architecture. The CABS ADC is a hybrid structure between the Flash ADC and the successive approximation register (SAR) ADC, capable of achieving excellent energy per conversion in the order of femto Joules. The architecture relies on a post fabrication calibration strategy to correct for process variation tolerances (PVT) and establish comparator threshold levels.

From simulation results the 8-bit ADC is capable of achieving a resolution of 7.98 bits at DC with a maximum frequency of operation of 20 MHz and an excellent figure of merit (FOM) of only 15.8 fJ per conversion. The input range is 600 mV differential, and the integral nonlinearity (INL) and the differential nonlinearity (DNL) are within 1/2LSB. The effective resolution bandwidth (ERBW) achieved is 25MHz with a signal to noise and distortion ratio (SINAD) of 49.1 dB and a spurious free dynamic range (SFDR) of 66.3dB. The core power consumption without output latches and drivers is only 122 μW for a sampling frequency of 20 MHz. The ADC was fabricated in a 0.13 μm IBM CMOS eight metal layer process (CMRF8SF). The use of an external sample-and-hold (SAH) in the measurement phase of the fabricated ADC places an upper limit on the maximum frequency of operation of the ADC. The measured FOM at a sampling frequency of 25 MHz is 15 fJ with a core power consumption of 100 μW.Using a non-optimum calibration code the INL of the fabricated ADC was improved from 64 LSB to 11 LSB. The DNL was improved from -68 LSB to 14 LSB. The ENOB was improved to 5.1 bits from 3.1 bits. The SINAD was 32.3 dB and the SFDR was 35.7 dB for an input frequency of 50 kHz at a sampling frequency of 4 MHz.

Distributed Bidirectional Amplifiers in CMOS

This research was conducted along with Dr. Ziad El-Khatib as part of his Ph.D. program. From Ziad's abstract:

A highly-linear transmitter with fully-integrated broadband design linearization capabil- ity is required to address linearity improvements. When the input signal driven into the amplifier semiconductor is increased, the output is also increased until a point where dis- tortion products can no longer be ignored. The harmonics and higher order distortion of the output signal are generated by nonlinearities of MOSFET devices. In response to the need to correct the broadband distributed amplifier (DA)’s nonlinear distortion, a num- ber of DA linearization techniques have been developed. However, most of the published DA linearization methods reported do not provide fully-integrated distortion cancellation techniques with large third-order intermodulation (IM3) distortion reduction.


The main contributions of this thesis research is the realization a fully-integrated high- frequency active broadband linearizer for large IM3 distortion cancellation and spectral regrowth reduction in standard CMOS technology.


In this thesis, we demonstrate a fully-integrated fully-differential linearized CMOS dis- tributed bidirectional amplifier that achieves large IMD3 distortion reduction over broad- band frequency range for both RF paths. The proposed linearized bidirectional DA has the drain and gate transmission-lines stagger-compensated. Reducing the DA IM3 distortion by mismatching the gate and drain LC delay-line ladders. The proposed fully-differential linearized DA employs a cross-coupled compensator transconductor to enhance the linearity of the DA gain cell with a nonlinear drain capacitance compensator for wider linearization bandwidth. The proposed linearized CMOS bidirectional DA achieves a measured IM3 distortion reduction of 20 dB with frequency of operation from 0.1 GHz to 9.5 GHz and a two-way amplification of 5 dB in both RF directions. The proposed linearized DA is imple- mented in 0.13μm RF CMOS process for use in highly-linear broadband communication.

A Predistortion Circuit for Direct Modulated Lasers for Radio over Fiber Applications

This research was conducted with Dr. Zhan Xu as part of his Ph.D. program. This research was highly theoretical at the onset, involving Volterra series representations of laser models. By the conclusion of the research, a fully functional laser pre-distortion integrated circuit was implemented and tested. In Dr. Xu's own words:

In radio over fiber systems, a linear optical transmitter is desirable in order to achieve an extended signal dynamic range. This thesis introduces and discusses a predistortion- compensation linearization technique to improve the optical transmitter’s linearity. In order to compensate for the second and the third order laser distortions, the predistorter’s quadratic and cubic law circuits are required to work at up to 2 or 3 times the carrier frequency. In this thesis, an alternative design approach is proposed to relieve the band- width requirement of the predistortion circuits. This approach uses multiple tank circuits to approximate the frequency profile shaping filters in the frequency band of interest. At the same time, tunability is provided to account for the changes of the laser’s distortion behavior due to component variations, thermal effects and aging. In order to tune the predistortion circuit adaptively, a calibration algorithm was proposed and implemented for minimizing the laser distortion. This algorithm is based on multiple variable feedback, which directly processes the RF signal and does not require a DSP unit or an optimization routine. This suggests a potential complete analog implementation with less circuit com- plexity. A prototype predistorter IC has been designed using 0.18 μm CMOS technology. It operates near 2GHz for demonstration purpose and has more than 300MHz linearized bandwidth. 5 to 15 dB reduction of the second harmonic distortion and the third order intermodulation distortion can be obtained.